This is a LoRA (Low-Rank Adaptation) adapter fine-tuned on meta-llama/Llama-2-7b-chat-hf for Verilog/RTL code generation tasks, specifically optimized for FIFO (First-In-First-Out) hardware design generation.

Key Features

Base Model: meta-llama/Llama-2-7b-chat-hf
Task: Verilog/RTL Code Generation
Specialization: FIFO hardware design
Method: LoRA (Low-Rank Adaptation)
Training: Fine-tuned on Elinnos FIFO dataset

Usage

Loading the Model

python

from transformers import AutoTokenizer, AutoModelForCausalLM
from peft import PeftModel
import torch

# Load base model
base_model = AutoModelForCausalLM.from_pretrained(
    "meta-llama/Llama-2-7b-chat-hf",
    torch_dtype=torch.float16,
    device_map="auto"
)

# Load LoRA adapter
model = PeftModel.from_pretrained(
    base_model,
    "varsha-de/llama2-7b-chat-verilog-fifo-lora"
)

# Load tokenizer
tokenizer = AutoTokenizer.from_pretrained("varsha-de/llama2-7b-chat-verilog-fifo-lora")
tokenizer.pad_token = tokenizer.eos_token

Generating Verilog Code

python

def generate_verilog(prompt):
    # Format prompt using the training format
    system_msg = "You are Elinnos RTL Code Generator v1.0, a specialized Verilog/SystemVerilog code generation agent. Your role: Generate clean, synthesizable RTL code for hardware design tasks. Output ONLY functional RTL code with no $display, assertions, comments, or debug statements."
    formatted_prompt = f"<|system|>\n{system_msg}</s>\n<|user|>\n{prompt}</s>\n<|assistant|>\n"
    
    inputs = tokenizer(formatted_prompt, return_tensors="pt").to(model.device)
    
    with torch.no_grad():
        outputs = model.generate(
            **inputs,
            max_new_tokens=512,
            temperature=0.0,
            do_sample=False,
            pad_token_id=tokenizer.eos_token_id,
            eos_token_id=tokenizer.eos_token_id,
        )
    
    decoded = tokenizer.decode(outputs[0], skip_special_tokens=False)
    
    # Extract assistant reply only
    if "<|assistant|>" in decoded:
        decoded = decoded.split("<|assistant|>")[-1]
    if "</s>" in decoded:
        decoded = decoded.split("</s>")[0]
    
    return decoded.strip()

# Example usage
code = generate_verilog("Generate a FIFO with 8-bit width, depth 4")
print(code)

Training Details

Base Model: meta-llama/Llama-2-7b-chat-hf
LoRA Rank (r): 16
LoRA Alpha: 32
Target Modules: q_proj, k_proj, v_proj, o_proj
Training Dataset: Elinnos FIFO corrected samples

Limitations

This is a LoRA adapter and requires the base model to function
Specialized for Verilog/RTL code generation, particularly FIFO designs
May require access to the base model (meta-llama/Llama-2-7b-chat-hf) which is gated

Citation

If you use this model, please cite:

bibtex

@misc{llama2_7b_chat_verilog_fifo_lora},
  author = {HF_USERNAME},
  title = {llama2-7b-chat-verilog-fifo-lora},
  year = {2026},
  publisher = {Hugging Face},
  howpublished = {\url{https://huggingface.co/varsha-de/llama2-7b-chat-verilog-fifo-lora}}
}