T10 frozen-baseline local competition package
This is an unpublished local competition-package candidate for the Modular
Arithmetic Challenge. It routes 1,025--2,048-bit primes to the frozen T10
bit-axis bidirectional-GRU expert. The frozen T1--T9 checkpoints and inherited
component files are copied byte-for-byte; the root manifest, model entry point,
configuration, and README are intentionally replaced for the integrated T10
package.
This package does not change the scientific result:
- research status:
ROLLOUT_MEASURED_BELOW_PROMOTION
- scientific admission:
SCIENTIFIC_ADMISSION_BLOCKED
- frozen one-step result: 999,990 / 1,000,000
- frozen fresh T10 rollout: 9,753 / 10,000 (97.53%)
The package exists only to measure the frozen baseline against the direct
competition-facing local checks. A local package audit cannot promote the
scientific result or change the historical scientific router.
Authorization boundary
The authorized scope is package construction and an RTX 4070 local package
audit. This artifact is not public, has not been evaluated from an immutable
Hugging Face revision, has not passed an external sandbox run, and has not
been officially submitted. Upload, publication, and submission require a
separate explicit approval.
Fixed inference schedule
T10 preprocessing produces bounded 4,096-bit representations of both raw
operands and a fixed 2,048-bit representation of the raw prime. Before the
first learned call, a raw-only width bucket is fixed independently for each
operand. Each bucket is the smallest of 64, 128, 256, 512, 1,024, 2,048, or
4,096 bits containing that operand.
- The
raw_a bucket updates a learned residue with multiplier one.
- The
raw_b bucket updates the product state using that learned fixed-width
residue tensor as the multiplier.
The radix is 2 and every learned transition is hard-thresholded to an explicit
binary residue. Model predictions do not determine digit tokens, order,
indices, masks, branches, loop bounds, padding, trimming, or schedule length.
Each width bucket depends only on the corresponding raw operand bit length.
Preprocessing does not deterministically compute either operand modulo p.
Frozen T10 expert
Each bit position receives state, multiplier, and prime features. A two-layer
bidirectional GRU uses hidden size 128 per direction and a linear 256-to-1
head. The 470,849 parameters are shared across the bit axis.
The frozen T10 baseline was warm-started from the T9 checkpoint and trained
for 10,000 one-step AdamW updates on the T10 distribution: batch 128, BF16,
learning rate 0.001, weight decay 0.01, 250-step warmup, cosine decay,
gradient clipping 1.0, and seed 56002. No DAgger, STE, auxiliary loss,
architecture change, or unrolled BPTT was used.
T10 checkpoint SHA-256:
bfc6d21b67cb13e90e71861759759f9067989ee318330ebf4f4c62724efa1604
Frozen T9 warm-start checkpoint SHA-256:
4a4ccf809400e1f782676b78d8a92b4b31f775ac0d40540d80c067aafa83ae41
The competition-only builder pins the historical T10 evidence manifest,
historical source archive, T9 package build report, all T5--T10 checkpoints,
and every output artifact. It fails closed if the frozen below-promotion
scientific decision is changed.
artifact.
Prior work and acknowledgments
This project benefited from public technical discussion in the SAIR
Foundation
#Modular Arithmetic Challenge channel, including discussion by
Robby Sneiderman, Hongyue Lei, Marcos Costa Santos Carreira, and YZ about
learned recurrent arithmetic, fixed Horner schedules, rollout drift, width
robustness, and raw-input rules. Robby Sneiderman's
NeuralHorner was a methodological
reference.
The inherited T4 temporal-convolution path was informed by the public
XllentAI/modular_arithmetic
model card. The T5-T9 BiGRU code, fixed
raw_b_two_pass schedule, data, and
weights were independently designed or generated; no code, weights,
checkpoints, replay buffers, or generated artifacts from those references were
copied.
