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anasuriramkumar/
VLSI-Assistant-1.5B-GGUF

Name: VLSI-Assistant-1.5B-GGUF
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## Model Details

###Model Description

<!-- Provide a longer summary of what this model is. -->

This is a fine-tuned, 1.5-billion parameter causal language model specifically optimized to act as an Electronic Design Automation (EDA) and Design Verification (DV) copilot. The model has been quantized into a 1.6GB GGUF format for completely offline local execution via Ollama, LM Studio, or Portable AI setups. It is designed to assist hardware engineers with SystemVerilog module generation, UVM testbench structuring, and Physical Design troubleshooting.

- **Developed by:** Ram Kumar (blackai0)
- **Funded by [optional]:** Open Source / Community
- **Shared by [optional]:** Ram Kumar (blackai0)
- **Model type:** Causal Language Model (Fine-tuned, Quantized GGUF)
- **Language(s) (NLP):** English (en), SystemVerilog, Verilog
- **License:** Apache-2.0
- **Finetuned from model [optional]:** Qwen/Qwen2.5-Coder-1.5B

### Model Sources [optional]

<!-- Provide the basic links for the model. -->

- **Repository:** https://github.com/blackai0/VLSI-LLM-FineTuning
- **Paper [optional]:** N/A
- **Demo [optional]:** Local execution via Ollama / LM Studio

## Uses

<!-- Address questions around how the model is intended to be used, including the foreseeable users of the model and those affected by the model. -->

### Direct Use

<!-- This section is for the model use without fine-tuning or plugging into a larger ecosystem/app. -->

This model is intended for direct local use by hardware engineers, electronics students, and VLSI professionals to generate synthesizable RTL blocks (e.g., asynchronous FIFOs, frequency dividers), draft SystemVerilog Assertions (SVAs), and troubleshoot Physical Design challenges like Layout vs. Schematic (LVS) failures and IR drop.

### Downstream Use [optional]

<!-- This section is for the model use when fine-tuned for a task, or when plugged into a larger ecosystem/app -->

Integration into local EDA workflows, developer environments (VS Code / Neovim), and offline chat interfaces (Ollama, LM Studio, Open WebUI) to act as an offline hardware copilot without exposing proprietary RTL to third-party cloud endpoints.

### Out-of-Scope Use

<!-- This section addresses misuse, malicious use, and uses that the model will not work well for. -->

The model should not be used as a replacement for functional simulation, linting, formal verification, or synthesis tools. It does not have access to proprietary foundry process design kits (PDKs) and is not validated for direct tape-out production without human engineer verification. It is also not intended for general-purpose conversational tasks outside the domain of IC design.

## Bias, Risks, and Limitations

<!-- This section is meant to convey both technical and sociotechnical limitations. -->

While fine-tuned for hardware design, the model is subject to hallucinations and may occasionally generate syntactically correct but functionally flawed logic under complex corner cases. Because vendor-specific constraints are proprietary, the model relies on general standard cell and ASIC design methodologies rather than specific foundry rules.

### Recommendations

<!-- This section is meant to convey recommendations with respect to the bias, risk, and technical limitations. -->

Users (both direct and downstream) should be made aware of the risks, biases and limitations of the model. Users should treat the model as a drafting and educational aid, and always compile, simulate, and run regressions on generated hardware descriptions before integrating them into larger SoC architectures.

## How to Get Started with the Model

Use the code below to get started with the model.

**Using Ollama:**
1. Create a `Build.txt` file:
```text
FROM chip_model.gguf
TEMPLATE """{{ if .System }}<|im_start|>system
{{ .System }}<|im_end|>
{{ end }}{{ if .Prompt }}<|im_start|>user
{{ .Prompt }}<|im_end|>
{{ end }}<|im_start|>assistant
"""
SYSTEM "You are an expert design verification engineer and IC designer specializing in SystemVerilog."
PARAMETER temperature 0.2

Build and run locally:

powershell

ollama create vlsi-assistant -f Build.txt
ollama run vlsi-assistant

Training Details

Training Data

The model was fine-tuned on a domain-specific dataset curated for digital logic design, SystemVerilog RTL syntax, UVM testbench architectures, SVAs, and Physical Design concepts, extending its base training of 5.5 trillion tokens.

Training Procedure

Preprocessing [optional]

Training Hyperparameters

Training regime: QLoRA (Quantized Low-Rank Adaptation) precision fine-tuning, subsequently merged with base weights, and converted to GGUF format via llama.cpp.

Speeds, Sizes, Times [optional]

Model Size: 1.6 GB
Parameters: 1.54 Billion
Context Length: 32,768 tokens

Evaluation

Testing Data, Factors & Metrics

Testing Data

Domain-specific prompts covering RTL implementation (e.g., clock frequency divider by 3 with a 50% duty cycle), assertion writing for asynchronous FIFOs, and physical design debugging scenarios.

Factors

Synthesizability of Verilog/SystemVerilog output, logic correctness, and adherence to IEEE 1800 SystemVerilog standards.

Metrics

Functional validity of generated RTL blocks and proper syntax/structure of UVM constructs to ensure practical usability for verification engineers.

Results

The fine-tuned model demonstrates strict adherence to Verilog/SystemVerilog standards and successfully reduces general-purpose conversational verbosity in favor of concise, synthesizable code output.

Summary

An accurate, lightweight, 1.5B parameter local copilot optimized for offline IC design and verification tasks.

Model Examination [optional]

Benchmarked locally on edge hardware with low inference latency and deterministic outputs using a low temperature configuration (0.2).

Environmental Impact

Carbon emissions can be estimated using the Machine Learning Impact calculator presented in Lacoste et al. (2019).

Hardware Type: Consumer GPU / Local CPU
Hours used: Lightweight fine-tuning and quantization execution time
Cloud Provider: N/A (Local / Edge compute)
Compute Region: Local
Carbon Emitted: Negligible due to lightweight 1.5B parameter architecture and offline execution

Technical Specifications [optional]

Model Architecture and Objective

Decoder-only Transformer architecture with Grouped-Query Attention (GQA) and Rotary Position Embeddings (RoPE), containing 28 layers and 1536 hidden dimensions, optimized for causal language modeling on hardware description languages.

Compute Infrastructure

Runs locally using Ollama or LM Studio on edge hardware without cloud dependency.

Hardware

Standard edge consumer hardware (CPU or GPU-accelerated) with at least 2 to 4 GB of available system RAM / VRAM.

Software

PyTorch
Hugging Face Transformers
llama.cpp
Ollama / LM Studio

Citation [optional]

BibTeX:

bibtex

@misc{vlsi_llm_finetuning_2026,
  author = {Ram Kumar},
  title = {VLSI-LLM-FineTuning: Specialized LLM for VLSI and SystemVerilog Design},
  year = {2026},
  publisher = {GitHub},
  url = {[https://github.com/blackai0/VLSI-LLM-FineTuning](https://github.com/blackai0/VLSI-LLM-FineTuning)}
}

APA:

Kumar, R. (2026). VLSI-LLM-FineTuning: Specialized LLM for VLSI and SystemVerilog Design. GitHub. https://github.com/blackai0/VLSI-LLM-FineTuning

Glossary [optional]

EDA: Electronic Design Automation
DV: Design Verification
SVA: SystemVerilog Assertions
UVM: Universal Verification Methodology
GGUF: GPT-Generated Unified Format
RTL: Register-Transfer Level
LVS: Layout vs. Schematic

More Information [optional]

This model enables hardware engineers to utilize AI-assisted coding and verification completely offline, eliminating the risk of leaking proprietary hardware designs to third-party endpoints.

Model Card Authors [optional]

Ram Kumar (blackai0)

Model Card Contact

GitHub: https://github.com/blackai0/VLSI-LLM-FineTuning

anasuriramkumar/VLSI-Assistant-1.5B-GGUF