Model Details

Property	Value
Base Model	Qwen/Qwen2.5-Coder-3B-Instruct
Fine-tuning Method	QLoRA (4-bit) via Unsloth
LoRA Rank	16
LoRA Alpha	32
Training Dataset	ADI2005/spice-circuits-finetune-v2
Dataset Size	7,410 entries (2,910 real + 4,500 synthetic)
Training Hardware	NVIDIA A100
Training Time	~35 minutes (3 epochs)
Final Training Loss	0.2694
SPICE Compatibility	ngspice

What It Does

Given a plain English description of an analog or digital circuit, the model generates a complete, valid SPICE netlist including:

Component definitions and node connections
.MODEL statements for transistors, diodes, and MOSFETs
Appropriate analysis commands (.AC, .DC, .TRAN, .OP)
.END termination

Validation Results

Tested on 5 circuit types after training — 5/5 passed PySpice syntax validation:

Circuit	Result
Low-pass RC filter	✅ Pass
NPN BJT common-emitter amplifier	✅ Pass
CMOS inverter	✅ Pass
Zener voltage regulator	✅ Pass
Full-wave bridge rectifier	✅ Pass

Usage

python

from unsloth import FastLanguageModel

model, tokenizer = FastLanguageModel.from_pretrained(
    model_name="ADI2005/qwen-spice-lora-v2",
    max_seq_length=2048,
    dtype=None,
    load_in_4bit=True,
)
FastLanguageModel.for_inference(model)

SYSTEM_PROMPT = """You are an expert analog circuit designer and SPICE netlist generator. 
When given a circuit description, you generate a complete, valid, simulation-ready SPICE netlist 
compatible with ngspice. Always include component definitions, node connections, model statements 
where needed, and an analysis command. End every netlist with .END"""

messages = [
    {"role": "system", "content": SYSTEM_PROMPT},
    {"role": "user", "content": "Design a low-pass RC filter with a cutoff frequency of 1kHz."},
]

input_ids = tokenizer.apply_chat_template(
    messages, tokenize=True, add_generation_prompt=True, return_tensors="pt"
).to("cuda")

outputs = model.generate(
    input_ids=input_ids,
    max_new_tokens=512,
    temperature=0.1,
    do_sample=True,
    pad_token_id=tokenizer.eos_token_id,
)

response = tokenizer.decode(outputs[0][input_ids.shape[1]:], skip_special_tokens=True)
print(response)

Training Dataset

Trained on ADI2005/spice-circuits-finetune-v2 — 7,410 instruction-output pairs covering 7 circuit families:

Resistive networks
RC circuits (low-pass, high-pass, band-pass filters)
RLC circuits
Diode circuits (rectifiers, clippers, clamps)
BJT amplifiers and switches
MOSFET circuits (CMOS logic, amplifiers)
Op-amp circuits (inverting, non-inverting, integrators, comparators)

All entries validated with PySpice before training.

Limitations

Component values are not always calculated precisely for a given specification (e.g., exact cutoff frequency). The topology will be correct but values may need tuning.
Best results on circuit types covered by the training set. Novel or exotic topologies may produce lower quality outputs.
Designed for ngspice compatibility. LTSpice-specific syntax is not guaranteed.

Roadmap

V3 dataset with spec-to-value calculated entries for filter and amplifier circuits
PySpice validation + retry loop at inference time
RAG layer for out-of-distribution prompts
Schematic generation via Weave integration