Verixa Dataset — HDL/RTL/UVM Training Data for LLMs105,340 deduplicated, quality-filtered samples for fine-tuning LLMs on chip design tasks:
Verilog RTL, UVM verification, SystemVerilog assertions, SystemC, EDA scripting, engineering workflow reasoning.
from datasets import load_dataset
dataset = load_dataset('vyomaalabs/verixa-dataset', split='train')
Apache-2.0 (all source repositories)
