Multi-scale, PDK-conditioned EDA training dataset. 275K designs across 3 PDKs (Sky130, GF180MCU, ASAP7), 5 frequency targets, full RTL-to-GDS pipeline.
technology/ - Cell library, layer stack, via definitions, design rules, RC parameters per PDK
geometry_patches/ - 10x10um layout tiles with wire/via/pin/cell coordinates
physics_labels/ - Per-segment R, C, coupling capacitance from SPEF
drc_labels/ - Legal/illegal geometry patterns with… See the full description on the dataset page:
https://huggingface.co/datasets/Xenn007/synth-layout-v1.