A synthetic dataset of 4,754 VHDL design-testbench pairs for LLM fine-tuning and digital design verification research. Testbenches were generated using DeepSeek-V3 and validated for simulatability using GHDL.
The dataset pairs real VHDL designs (from rtl-llm/vhdl_github_deduplicated, cleaned VHDL-only subset) with synthetic testbenches in two complementary formats:
Design-Testbench Pairs
4,754… See the full description on the dataset page:
https://huggingface.co/datasets/NOKHAB-Lab/LLM_4_TestBench.
