A rigorous benchmark for evaluating LLM-generated Verilog HDL. Built by adapting proven software benchmarks (AAPP, MBPP, HumanEval) to the hardware domain,
translate's 1,192 problems into hardware design tasks, measuring both compilation success and functional verification.
Repository:
https://github.com/ani-ani/verifyverilog-dataset
Paper: TBD
task_id
Serial number identifier from the original programming… See the full description on the dataset page:
https://huggingface.co/datasets/Ani-DNN/Verify-Verilog.