An MLX conversion and 4-bit quantization (group size 64) of Nanbeige/Nanbeige4.2-3B — a 3-billion-parameter Looped Transformer (num_loops=2, weight-shared over 22 layers for an effective depth of 44). Produced by the independent nanbeige-mlx project; not affiliated with the Nanbeige team.

Load (no conversion step)

python

from nanbeige_mlx import pull
import mlx_lm
model, tok = mlx_lm.load(pull("4bit"))

Weights arrive on first use and are cached in ~/.cache/huggingface.

KV-cache ceiling (a real cost of the looped design)

The looped architecture needs num_loops * num_hidden_layers = 44 KV slots. At full context that is 44 x 8 KV-heads x 128 dim x 2 (K+V) x 262144 positions x 2 bytes ~= 47 GB — unreachable on a 16 GB machine. Because this model supplies make_cache, mlx-lm's --max-kv-size knob is inert; use --kv-bits to reduce KV precision instead.

Fidelity of the port

This quant is produced by a from-scratch MLX port of the looped architecture, checked against the HuggingFace reference. The headline finding carries over verbatim from the port's documentation, and must read identically wherever it appears (repo README, model card, investigation log):

Bottom line: the source of the logit gap is documented-open, not blocking. Six candidate causes are ruled out by measurement (the seventh, "RoPE runs in bf16," was killed by a bit-identical upcast experiment — mx.fast.rope is fp32-internal regardless of input dtype). The [1,1,5,6] mask shape is a red herring: the 6th column is HF's past_seen_tokens + sequence_length + 1 boilerplate for StaticCache sizing, present in every Llama-family model, and eager attention slices it to [:,:,:,:L] before use — nothing to do with num_loops. The gap does not affect behavior on the agentic suite. Bit-exact parity is not claimed and not expected in bf16. Full record: docs/investigation-log.md.

License

Apache-2.0 (the upstream license; quantization is a modification under §4(d)). The nanbeige.py model definition is MIT-licensed source from nanbeige-mlx. See LICENSE and NOTICE.

jishnuvenugopal/Nanbeige4.2-3B-mlx-4bit

Nanbeige4.2-3B MLX (4-bit)

Load (no conversion step)

KV-cache ceiling (a real cost of the looped design)

Fidelity of the port

License

jishnuvenugopal/
Nanbeige4.2-3B-mlx-4bit