chipcraftx-rtlgen-7b is the local RTL generation engine powering ChipCraftX -- an AI platform that converts natural language specifications into synthesizable Verilog. It achieves 36.5% on VerilogEval-Human standalone, and 98.7% (154/156) within the full ChipCraftX hybrid pipeline.

Available Quantizations

File	Quant	Size	Quality	Use Case
`chipcraftx-rtlgen-7b-q4_k_m.gguf`	Q4_K_M	4.4 GB	Good	Low-VRAM GPUs, CPU inference
`chipcraftx-rtlgen-7b-q5_k_m.gguf`	Q5_K_M	5.1 GB	Very Good	Balanced quality/speed
`chipcraftx-rtlgen-7b-q8_0.gguf`	Q8_0	7.6 GB	Excellent	High-quality, fits most GPUs
`chipcraftx-rtlgen-7b-f16.gguf`	F16	15 GB	Lossless	Full precision, identical to safetensors

Recommended: q8_0 for best quality/size tradeoff. Use q4_k_m if VRAM-constrained.

Usage with Ollama

Download a GGUF file from this repo
Create a Modelfile:

FROM ./chipcraftx-rtlgen-7b-q8_0.gguf
TEMPLATE """{{ if .System }}<|im_start|>system
{{ .System }}<|im_end|>
{{ end }}{{ range .Messages }}{{ if eq .Role "user" }}<|im_start|>user
{{ .Content }}<|im_end|>
<|im_start|>assistant
{{ else if eq .Role "assistant" }}{{ .Content }}<|im_end|>
{{ end }}{{ end }}"""

SYSTEM """You are ChipCraft-RTL, an expert Verilog/SystemVerilog design engineer.
Generate synthesizable, lint-clean RTL that exactly matches the specification.
Rules:
- Output ONLY Verilog/SystemVerilog code (no prose, no markdown fences).
- Use reg and wire types ONLY -- NEVER use logic.
- Use always @(posedge clk) and always @(*) -- NEVER use always_ff or always_comb.
- Use localparam for constants -- NEVER use typedef enum.
- Module name MUST be TopModule."""

PARAMETER stop "<|im_end|>"
PARAMETER num_ctx 4096

Import and run:

bash

ollama create chipcraftx-rtlgen-7b -f Modelfile
ollama run chipcraftx-rtlgen-7b "Implement a 4-bit counter with synchronous reset. module TopModule(input clk, input reset, output [3:0] count);"

Usage with llama.cpp

bash

./llama-cli -m chipcraftx-rtlgen-7b-q8_0.gguf \
  --chat-template chatml \
  -p "Implement a module named TopModule that behaves like a wire. input in, output out." \
  -n 512 --temp 0.2

Benchmark Results

See chipcraftx-rtlgen-7b for full benchmark details.

Model	Pass Rate (VerilogEval-Human)
VeriGen (16B)	26.0%
chipcraftx-rtlgen-7b (standalone, 7B)	36.5%
RTLCoder (7B)	37.0%
ChipCraftX hybrid system	98.7%

About

Built by ChipCraftX. Fine-tuned from Qwen2.5-Coder-7B-Instruct on 76,811 proprietary Verilog samples.

Citation

bibtex

@misc{chipcraftx-rtlgen-7b,
  title={chipcraftx-rtlgen-7b: Local RTL Generation Engine for ChipCraftX},
  author={Eryilmaz, Cagri},
  year={2026},
  publisher={HuggingFace},
  url={https://huggingface.co/chipcraftx-io/chipcraftx-rtlgen-7b}
}

chipcraftx-io/chipcraftx-rtlgen-7b-GGUF

chipcraftx-rtlgen-7b-GGUF