The repository provides the model in FP32 ONNX format. Both supported runtimes automatically cast the FP32 model to INT8 at load time for optimised NPU execution — no separate quantization step is required.
INT8 execution is handled automatically by the NPU runtime — no additional quantized model file is needed.
Performance
All HIL results were measured on Renesas R-Car X5H physical hardware.
The FP32 ONNX model is auto-cast to INT8 by the runtime before NPU execution.
PPA Estimator results are software estimates based on model characteristics and hardware configuration.
Benchmark configuration: Single NPU · Single AI Core · Input: 3 × 224 × 224 · Batch size: 1
Inference Latency & Throughput
Runtime
Precision
Device
Latency (ms)
Throughput (fps)
Type
ORT Custom NPU EP
INT8 (auto)
X5H · 1× NPU · 1 Core · 850 MHz
2.02
495.0
Measured
MWMX Runtime
INT8 (auto)
X5H · 1× NPU · 1 Core · 850 MHz
1.05
952.4
Measured
PPA Estimator
INT8
X5H · 1× NPU · 1 Core · 1066 MHz
1.1
—
Estimated
Accuracy (ImageNet ILSVRC2012 Validation Set — 50 000 images)
Runtime / Precision
Top-1 Accuracy
Top-5 Accuracy
Notes
FP32 reference
75.1 %
92.3 %
ORT, FP32 native execution
ORT Custom NPU EP (INT8)
74.0 %
93.0 %
INT8 auto-cast, NPU execution
MWMX Runtime (INT8)
—
—
Not yet measured
Runtime Details
ONNX Runtime – Custom NPU Execution Provider
Engine: ONNX Runtime with Renesas Custom NPU Execution Provider
Input format: FP32 ONNX (.onnx)
NPU execution precision: INT8 (auto-cast at load time)
1import onnxruntime as ort
2import numpy as np
34# Runtime auto-casts FP32 model to INT8 for NPU execution5providers =[("ReneasNPUExecutionProvider",{}),"CPUExecutionProvider"]6sess = ort.InferenceSession("fp32/mobilenetv2-12.onnx", providers=providers)78# Input: ImageNet-normalized image, shape (1, 3, 224, 224), dtype float329input_data = np.random.randn(1,3,224,224).astype(np.float32)10outputs = sess.run(None,{"input": input_data})11class_scores = outputs[0]# shape (1, 1000)
MWMX Runtime
Refer to the Renesas MWMX Runtime documentation for compilation and inference scripts targeting the NPX6 NPU on R-Car X5H. The MWMX toolchain ingests the FP32 ONNX model and automatically compiles it for INT8 NPU execution.
Benchmark Methodology
HIL runs: Hardware-in-the-loop — measured on physical R-Car X5H silicon; single NPU, single AI core, 850 MHz NPU clock
Estimation: PPA Estimator software estimate; single NPU, single AI core, 1066 MHz NPU clock
Precision: FP32 ONNX input; INT8 execution (auto-cast by runtime)
Latency: Median over 1000 consecutive inference runs with warm cache
Throughput: Computed as 1000 / latency_ms
Accuracy: Evaluated on the ImageNet ILSVRC2012 validation set (50 000 images); softmax Top-1 and Top-5
