OpenVINO IR of Qwen/Qwen2.5-Coder-1.5B-Instruct, weight-compressed to INT4, symmetric, group size 128. Converted specifically to run on the Intel Core Ultra Series 1 (Meteor Lake) NPU, where it serves a dual role: request router and FIM autocomplete.

On Intel Core Ultra Series 1, the NPU supports only symmetrically quantized channel-wise or group-wise INT4 weights — asymmetric INT4 trips the NPU compiler (vpux verifier: duplicated names on the dequantize subgraph). This build is symmetric, group size 128, which satisfies the Series-1 requirement. On the NPU it serves a dual role — request router and FIM autocomplete — running behind its own inference lock so it never queues behind GPU chat/agent turns; a CACHE_DIR blob cache cuts NPU load time.

Serving and tooling: core-ultra-llm-server.

optimum-cli export openvino -m Qwen/Qwen2.5-Coder-1.5B-Instruct \
    --weight-format int4 --sym --group-size 128 \
    Qwen2.5-Coder-1.5B-int4-symg128-ov

transformers==4.57.6, optimum-intel (OpenVINO exporter). Self-contained: includes the OpenVINO model IR plus the OpenVINO tokenizer/detokenizer IRs.

Apache-2.0, inherited from the base model.